This non-provisional application claims the benefit of the provisional application filed with the United States Patent and Trademark Office as Ser. No. 61/148,059 entitled “Semiconductor Chips Including Passivation Layer Trench”, filed Jan. 29, 2009.
The present invention relates to electrical circuits, and more specifically, to reducing the effects created when a wafer containing multiple integrated circuits is cut.
In integrated circuits formed on a Si substrate, delamination, driven by coefficient of thermal expansion (CTE) mismatch between the Si substrate and package, is a dominant failure mode. This problem is exacerbated at bi-material interfaces such as interfaces between underfill and die passivation or underfill and substrate solder mask. The problem may be even worse if the underfill is imperfect.
A delamination initiated from the die edge takes the form of an interfacial microcrack. In addition, initial delamination may also be caused by formation of microcracks (possible during dicing) or voids during dispensing process or surface contamination. As some initial underfill flaws are unavoidable, preventing flaw propagation as an unstable crack is important.